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This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.

Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC)

Introduction.- Synthesis Basics.- Timing Analysis and Constraints.- SDC Extensions through Tcl.- Clocks.- Generated Clocks.- Clock Groups.- Other Clock Characteristics.- Port Delays.- Completing Port Constraints.- False Paths.- Multi Cycle Paths.- Combinatorial Paths.- Modal Analysis.- Managing Your Constraints.- Miscellaneous SDC Commands.- XDC: Xilinx Extensions To SDC.