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This book introduces several novel approaches to pave the way for the next generation of integrated circuits, which can be successfully and reliably integrated, even in safety-critical applications. The authors describe new measures to address the rising challenges in the field of design for testability, debug, and reliability, as strictly required for state-of-the-art circuit designs. In particular, this book combines formal techniques, such as the Satisfiability (SAT) problem and the Bounded Model Checking (BMC), to address the arising challenges concerning the increase in test data volume, as well as test application time and the required reliability. All methods are discussed in detail and evaluated extensively, while considering industry-relevant benchmark candidates. All measures have been integrated into a common framework, which implements standardized software/hardware interfaces.

Design for Testability, Debug and Reliability: Next Generation Measures Using Formal Techniques

Introduction.- Integrated Circuits.- Formal Techniques.- Embedded Compression Architecture for Test Access Ports.- Optimization SAT-based Retargeting for Embedded Compression.- Reconfigurable TAP Controllers with Embedded Compression.- Embedded Multichannel Test Compression for Low-Pin Count Test.- Enhanced Reliability using Formal Techniques.- Conclusion and Outlook.