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This book describes a circuit architecture for converting real analog signals into a digital format, suitable for digital signal processors. This architecture, referred to as multi-stage noise-shaping (MASH) Continuous-Time Sigma-Delta Modulators (CT-DeltaSigmaM), has the potential to provide better digital data quality and achieve better data rate conversion with lower power consumption.  The authors not only cover MASH continuous-time sigma delta modulator fundamentals, but also provide a literature review that will allow students, professors, and professionals to catch up on the latest developments in related technology.

Design Techniques for Mash Continuous-Time Delta-Sigma Modulators

Introduction.- Analog-To-Digital and Digital-To-Analog Converters.- Delta-Sigma Modulators.- Design Considerations Of Mash CT-DeltaSigmaM.- A 43 mW MASH 2-2 CT DeltaSigma Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40nm CMOS.- A 50-MHz BW 67.3-dB SNDR MASH 1-1-1 CT DeltaSigma Modulator with FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS.- A 4-Bit Continuous-Time DeltaSigma Modulator with Fully Digital Quantizer Noise Reduction Algorithm Employing a 7-bit Quantizer.- Conclusion.