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Wafer-Level Testing and Test During Burn-In for Integrated Circuits

Wafer-Level Testing and Test During Burn-In for Integrated Circuits

Autorzy
Wydawnictwo Artech House, Inc.
Data wydania 20/02/2010
Wydanie Pierwsze
Forma publikacji eBook: Fixed Page eTextbook (PDF)
Język angielski
ISBN 9781596939905
Kategorie Inżynieria elektroniczna i komunikacyjna
licencja wieczysta
Produkt dostępny on-line
Typ przesyłki: wysyłka kodu na adres e-mail
E-Mail
zamówienie z obowiązkiem zapłaty
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Opis książki

Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this unique book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions.

Wafer-Level Testing and Test During Burn-In for Integrated Circuits

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